Configurable Processor Architectures: History and Trends

In this invited talk, we characterize the approaches taken to form customized processors using combinations of programmable processors and Field Programmable Gate Arrays (FPGAs). We investigate these approaches by considering how and where customization takes place. We consider approaches to customize within a processors ISA, and external to the ISA. We also consider how processor customization can be used to increase designer productivity by adopting more software centric design flows and higher levels of abstraction. Since its inception, researchers within reconfigurable computing have sought methods to enable the creation of configurable computing components to give performance levels close to those achievable with custom circuits, but with productivity levels more closely associated with software development. The discipline has witnessed many novel approaches to balance these seemingly contradictory goals. By far the most common approach started by extending a general purpose processors instruction set architecture (ISA) into the reconfigurable fabric. In these “inside the ISA” approaches, custom circuits were created and placed within the reconfigurable fabric to replace a series of less efficient assembler instructions. Instruction fusion was explored, where combinations of instructions such as multiply and add were replaced by a single multiply-add circuit. As the size of the FPGA devices grew, this inside the ISA approach was driven by Amdahl’s law. Instruction fusion was expanded to encompass a temporal to spatial transformation of loop bodies to exploit data level parallelism. To increase productivity within these approaches, the discipline witnessed an explosion in C to gates type efforts. These efforts targeted increased productivity by raising the level of abstraction at which the developer could evaluate, define, and create the custom ISA extensions. Creating custom ISA extensions is still a popular approach within reconfigurable computing today. FPGA technology has followed Moore’s law, with densities and capabilities of devices continuing grow. Each new generation has allowed the exploitation of yet more inside the ISA data and instruction level parallelism. The community now is witnessing an increase in the availability of configurable soft processor cores that can be tailored below and above the ISA. Soft processors allow the customization of pipeline stages, coprocessor circuits such floating point units, and caches. Customization still continues within the ISA through configurable vector processor support circuitry. These approaches continue to reduce the performance versus productivity gap by abstracting the physical reconfigurable fabric underneath more software centric modern parallel programming languages and compilers. New run time methods also allow custom ISAs to be created through just in time synthesis type methods. Platform FPGAs have further widened the use case spectrum by allowing a complete multiprocessor systems on chip architecture to be configured within a single FPGA device. This capability has spurred researchers to create new methods that exploit parallelism outside the ISA and processor, at higher system abstraction levels. These approaches extend the notion of a configurable processor architecture to creating systems with multiple processors, with the possibly of mixing general purpose and customized processors. Performance increases can target exploiting multiple threads along with more efficient circuits for each individual thread. Productivity increases follow from the expanded adoption of more traditional software protocol stacks, including middleware and operating system services. As the future unfolds, FPGA capabilities are merging with the general purpose computing community in allowing increased performance through parallelism across heterogeneous multicore systems. In this talk we will discuss the future of configuring custom processors within modern Platform FPGAs. We will provide a survey and lessons learned from earlier attempts, and then forecast how Platform FPGAs can serve as a substrate for next generation heterogeneous multi-processor systems on programmable chip architectures. We then outline the research challenges that will need to be addressed to make this vision a